The present invention relates, in general, to very large scale integration (VLSI) technology, and more particularly to a method of forming improved interconnections in VLSI devices.
The fabrication of integrated circuits is based on materials, processes, and design principles which constitute a highly developed technology, and which are well known in the industry. Monolithic circuits are the most fundamental form, wherein the entire circuit, including active and passive components, is formed in a monolithic body of semiconductor material. In another form, thin- or thick-film circuits are fabricated by depositing conductive or resistive films on an insulating substrate, and by imposing patterns on them to form an electrical network. Hybrids form a natural extension of the first two types, and contain passive and active devices, as well as monolithic integrated circuits assembled and interconnected on an insulating ceramic substrate common to all. Such circuits have application not only in linear devices such as amplifiers, but also in digital devices such as logic circuits and memories. More recently, integrated circuits have found application in microwave circuits, operating at extremely high frequencies, on the order of 15 GHz, and such applications rely heavily on hybrid circuit technology.
Techniques utilizing VLSI technology provide a large number of components, on the order of 10,000 individual circuit components, on a single integrated circuit chip, the components being interconnected to form complete systems or subsystems. The electrical interconnection of these integrated components is achieved, for example, by the evaporation of highly conductive thin films onto a silicon dioxide insulating layer formed on the integrated circuit. The most often used material for this purpose is aluminum, because of its high electrical conductivity and good adherence to the silicon dioxide surface. Resistive thin films such as tantalum, nickel-chromium alloys, and tin oxide are commonly used to form resistor patterns.
A variety of deposition techniques are available for forming thin-film layers on a dielectric substrate. Thus, vacuum evaporation is commonly used to deposit aluminum, gold, or silver conductive films. Cathode sputtering, vapor phase deposition, plating techniques, and anodization processes are also well known. The basic photomasking and etching techniques have been commonly utilized in patterning thin-film components, except that where multiple thin-film layers are produced, care must be taken in the choice of an etchant to make sure that the bottom film is not damaged by the patterning of the top layer. Furthermore, since photoresist is an organic polymer, it cannot withstand exposure to high temperatures, so that the deposition of some materials, which require high temperatures, is limited.
The basic requirement for the conductive films used for interconnections is that they should make good ohmic contact with the diffused components or other metallic films deposited on the device surface. The exposure of contact areas to ambient atmosphere often results in the formation of parasitic oxide layers over the chip area to be interconnected. Therefore, to provide good ohmic contact, the interconnecting metal must be chemically active so that it can be alloyed or sintered through these parasitic layers. As noted above, the most commonly used interconnection metal is aluminum, which can be readily alloyed into the silicon substrate, to form ohmic contacts.
If the required interconnection cannot be accomplished in one plane, different methods of producing crossovers are available, but when very high packing densities of devices are required, or if stray capacitances must be minimized, multi-layer metallization can be used. Such metallization involves depositing alternate layers of patterned interconnections separated by dielectric layers, and care must be taken to select materials that will have sufficient dielectric strength, volume resistivity, and thermal and mechanical stability to withstand the processing operations used to form the interconnections. Most multi-layer metal processes use aluminum as the interconnection metal. The multiple interconnection layers are themselves interconnected by way of via holes cut in the separating dielectric layer.
The reliability of interconnections is a serious problem in VLSI microcircuits, however, and particularly in submicron circuits, such as those designed for microwave frequencies, where the pitch of adjacent interconnection lines might be about 2 microns. This is due, in large part, to electromigration effects at high current densities.
Electromigration is a mass-transport effect which causes the atoms of the interconnection metal to migrate gradually toward the more positive end of the conductor. This phenomenon takes place along the grain boundaries of the metal interconnections, and results in the formation of voids in the interconnection pattern which may eventually lead to an open circuit. Such electromigration is enhanced at elevated temperatures. In addition, in the case of aluminum interconnections, chemical reactions between silicon or silicon dioxide and the aluminum layer can also result in breaks in the conductive interconnection pattern.
In addition to the foregoing problems, prior methods of providing interconnects often result in the need to pattern and etch metal films. This process is undesirable in submicron circuits, for the patterning and etching of deposited metal results in a non-planar surface, and thus makes multi-level interconnection difficult and expensive, since replanarization becomes necessary after each level. Because each such process step tends to reduce the yield of the process, the complexity of prior systems, as a practical matter, often limits such connections to two layers. Although conventional lift-off procedures can solve some of these problems in some circuits, it is next to impossible to fabricate a submicron metal line using such procedures.